Note: I am not affiliated with the project

  • dragontamer@lemmy.world
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    10 months ago

    Ehhhh… I’d recommend a Teensy instead, or a variety of other microprocessors. At $72, this is awful value. And there seems to be no specifications with regards to power-consumption.

    https://www.pjrc.com/store/teensy41.html

    Teensy 4.1 gives you Hardware Floating point, 100 MBit Ethernet, USB, 600MHz, 1024kB of SRAM, 7MB of Flash for like $35 and within ~100mA of current usage at this 600MHz speed, meaning it easily runs off of AA Batteries for over a day with just a bit of idle/sleep cycles.

      • dragontamer@lemmy.world
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        10 months ago

        On the contrary, RISC-V is typically bigger and less efficient than Cortex-M7 on the Teensy.

        There are 10-cent ARM Cortex M0+ processors (M0+ being the smallest ARM). M7 is kinda-small. ARM scales to different sizes and power-efficiencies.

        • Danny M@lemmy.escapebigtech.infoOP
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          10 months ago

          in this case the instruction set is extremely small (and includes open source verilog, so you could even fab it yourself)

          quote from the website:

          The CPU of the TKey is a modified version of PicoRV32, 32-bit RISC-V running at 18 MHz. Modifications includes a fast 32x32 multiplier implemented using the multiplier blocks in the iCE40 DSPs as well as a HW trap function.

          The supported instruction set supported by the CPU is a subset of RV32I. Specifically it includes compressed instructions, but excludes instructions for:

          • Counters
          • System
          • Synch
          • CSR access
          • Change level
          • Trap redirect
          • Interrupt
          • MMU

          The instruction set implemented by the CPU also includes multiplication instructions from the RV32IC_Zmmul (-march=rv32iczmmul) extension. Division is not supported.

          Any illegal, unsupported instruction will halt the CPU. The halted CPU is detected by the hardware, which will blink the RGB LED with red to indicate the error state. There is no way for the CPU to exit the trap state besides a power cycle of the device.

          Note that the CPU has no support for interrupts. No instructions, ports or logic.

    • BearOfaTime@lemm.ee
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      10 months ago

      Wow.

      I have no idea what I’d use it for (or even how to use it) but I want one!