It’s wild to read this classic 1991 paper that basically put the numbers behind the RISC vs. CISC flame wars. The authors wanted to figure out which processor architecture was actually better by comparing a RISC champ (MIPS M/2000) against a CISC heavyweight (VAX 8700).
To make it a fair fight, they picked these two specifically because their internal hardware pipelines were shockingly similar, even though the VAX was a massive, expensive beast and the MIPS was a sleek custom chip. This way, they could mostly blame the architecture itself for any performance difference, not the manufacturing tech.
The TLDR is that RISC absolutely crushed it. On average, the VAX had to burn through 2.7 times more CPU cycles to get the same work done. The whole RISC strategy was trading fewer, complex instructions for way simpler, fast ones. Even though the MIPS machine needed more instructions to finish a task, its cycles per instruction (CPI) were so much lower that it won by a huge margin.
The paper shows that the more complex a VAX instruction was (higher VAX CPI), the more simple MIPS instructions were needed to replace it, but the trade-off was always a big net win for RISC.
So why was MIPS so much better? The authors point to a few key architectural wins. First, MIPS had way more registers (32 general-purpose + 16 for floating-point) compared to the VAX’s 15, which meant it didn’t have to access slow memory as often. Second, basic operations like conditional branches were way faster on MIPS (1-2 cycles) than on the VAX (5 cycles), which was a huge deal. The MIPS architecture was also just smarter about keeping the pipeline full by using things like delay slots, which is basically doing useful work in moments that would have otherwise been wasted cycles—something the VAX couldn’t do.
The authors admit their study isn’t perfect, and they point out that compiler quality could have skewed the results and they only used a handful of programs for testing. But still, looking back, this paper was basically a prophecy for why modern CPUs, even from Intel, have a RISC-style core under the hood. It laid out the fundamental math for why the RISC approach was the future.
I don’t really see how what you detailed in your summary connects to your thesis. How are things like more registers and less cycles for branches related to using RISC over CISC? It reads more like the microarchitecture of the MIPS is better rather than the approach of the ISA.
I’m guessing you didn’t bother actually reading the paper, here are some relevant quotes from it:
This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks.
Performance comparisons across different computer architectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance.
We will do this by studying two machines, one from each architectural school, that are strikingly similar in hardware organization, albeit quite different in technology and cost.
There are strong organizational similarities between the VAX 8700 and the MIPS M/2000… Figure 1 shows that the pipelines match up quite closely, with the obvious exception of the VAX instruction decode stage.
…these two machines are very different in technology, size, and cost: the VAX processor is nine boards full of ECL gate arrays; the MIPS processor is one board with two custom CMOS chips.
…this paper shows that the resulting advantage in cycles per program ranges from slightly under a factor of 2 to almost a factor of 4, with a geometric mean of 2.7.
This factor [the RISC factor] ranges from just under 2 to just under 4, with a geometric mean of 2.66.
The RISC approach offers, compared with VAX, many fewer cycles per instruction but somewhat more instructions per program.
The correlation has a simple and natural explanation: given reasonable compilers, higher VAX CPI should correspond to a higher relative instruction count on MIPS.
The MIPS architecture has 32 (32-bit wide) general registers and 16 (64-bit wide) floating-point registers; VAX has 15 (32-bit wide) general registers… This can obviously lead to more memory references on the VAX…
The time for the simplest taken branch (or unconditional jump) on the VAX 8700 is five cycles. On MIPS, which has a delayed branch, it is one cycle if the delay slot is filled, and two otherwise.
The MIPS architecture allows instructions to be inserted in code positions that might otherwise be lost to pipeline delays… This ability is not present in the VAX architecture…
First, we cannot easily disentangle the influence of the compiler from the influence of the architecture. Thus, strictly speaking, our results do not compare the VAX and MIPS architectures per se, but rather the combination of architecture with compiler.
Second, we measured a rather small number of programs. Measurements that attempt to characterize machines broadly should be based on much more data.
…we believe that the fundamental finding will stand up: from the architectural point of view (that is, neglecting cycle time), RISC as exemplified by MIPS offers a significant processor performance advantage over a VAX of comparable hardware organization.
